Smartphones, tablets, and other portable electronics are everywhere. Most of these devices rely on a kind of flash memory known as NAND to meet consumer’s storage needs. Everyone wants their phone to hold more photos, more files, and more apps. But at the same time, we also want our devices to get smaller and less […]
Smartphones, tablets, and other portable electronics are everywhere. Most of these devices rely on a kind of flash memory known as NAND to meet consumer’s storage needs. Everyone wants their phone to hold more photos, more files, and more apps. But at the same time, we also want our devices to get smaller and less expensive. Device makers need storage solutions that offer increased density, without increasing the device’s cost per bit.
One possible solution to this problem is stacking NAND flash memory into vertical layers. This is known as a 3D NAND drive. These drives do not scale well in the long term, however, because they rely on poly-Si vertical channels. The conduction of these channels is hampered by a number of factors, including the Si grain size distribution, scattering events at grain boundaries, and charged defects. As a result, the required drive current decreases with each layer added to a 3D NAND drive, effectively limiting their capacity. This technical limitation must be overcome before 3D NAND drives can spur a storage revolution in portable electronics.
At imec, an internationally renowned nanoelectronics research center, we’ve been working on replacing the vertical poly-Si channel in 3D NAND drives with group III‑V compound semiconductors. This change could lead to devices with a higher drive current and larger cell stacks, allowing manufacturers to scale the drives sustainably.
The replacement of poly-Si channel with epitaxially grown In1‑xGaxAs is not straightforward and requires an adaptation of the Si-reference process flow. Given the selective nature toward Si of III-V epitaxial growth, a careful surface preparation is required to enable the proper channel formation. An appropriate tuning of In1‑xGaxAs precursors, in combination with growth temperature and flow ratio is also necessary to avoid selectivity issues. Since III‑V compounds have a low thermal budget, the formation of source and drain junctions need modifications with respect to Si‑reference flow.
The physical characterization required to understand the intrinsic material’s properties inside the channel is not trivial. For this purpose, we applied scalpel SPM, a dedicated nm-precise three-dimensional analysis technique based on electrical scanning probe microscopy. The direct 3D observation of the conductive path inside the vertical channel allowed the comparison of the transport for poly-Si and In1‑xGaxAs.
We recently integrated high-mobility In1‑xGaxAs as replacement of poly-Si channel in 3D NAND flash for the first time. The In1-xGaxAs channel is formed by Metal Organic Vapor Phase Epitaxy in a 45 nm diameter cylindrical hole via a gate-first, channel‑last approach. In addition, devices based on poly-Si and In1‑xGaxAs have been characterized by scalpel SPM bridging the electrical performance to the material structure at the nm-scale. These works, respectively presented at the last International Electron Devices Meeting 2015 and the Symposia on VLSI Technology and Circuits 2016, demonstrated that In1-xGaxAs-based devices have superior conduction properties. These improvements will make it possible to create 3D NAND storage with more layers per chip than the current 48-layer maximum. Removing this storage limitation could have tremendous implications, not just for phones but for all kinds of portable electronic devices in need of cheaper, more efficient storage
Electrical characterization and device integration
Physical characterization and 3D tomography